/* ads834x/config.h - Motorola ADS834x-PCI board configuration header */

/* Copyright 1984-2005 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,18dec03,dtr  adapted from ads827x config.h
*/

/*
This file contains the configuration parameters for the
Motorola MPC8349E ADS board.
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */


/* BSP version/revision identification, should be placed
 * before #include "configAll.h"
 */

#define BSP_VER_1_1		1
#define BSP_VER_1_2		1
#define BSP_VERSION		"1.2"
#define BSP_REV		 	"/0"

#ifdef INCLUDE_CARD_MPU
	#define  MPUA
#elif defined(INCLUDE_CARD_GEU)
	#define  GEUA
#elif defined(INCLUDE_CARD_XEU)
	#define  XGUA
#elif defined(INCLUDE_CARD_EPU)
	#define EPUA
       #define EPUB
#endif

/* Define Clock Speed and source  */

#define	FREQ_33_MHZ	 	 33000000
#define	FREQ_40_MHZ	 	 40000000
#define	FREQ_66_MHZ	 	 66000000
#define   FREQ_100_MHZ           100000000
#define   FREQ_133_MHZ           133333000    /*133000000*/
#define   FREQ_165_MHZ           165000000
#define   FREQ_266_MHZ           266000000
#define   FREQ_333_MHZ           333000000


/* ------- added by chengxiang ------- begin  */
#if 0
#define INCLUDE_TIMESTAMP
#define INCLUDE_PING
#define INCLUDE_TELNET
#define INCLUDE_NET_SHOW    
#define INCLUDE_FTP_SERVER	
#define INCLUDE_WDB_SYS
#define INCLUDE_SHELL 
#define INCLUDE_SYM_TBL_SYNC
#define INCLUDE_SPY
#define STANDALONE_NET
#define INCLUDE_SIGNALS
#define INCLUDE_ARP             
#define INCLUDE_PROXY_CLIENT
#define INCLUDE_PROXY_DEFAULT_ADDR
#define INCLUDE_PROXY_SERVER
#define INCLUDE_DOSFS_MAIN      /* dosFsLib (2) */
#define INCLUDE_DOSFS_FAT       /* dosFs FAT12/16/32 FAT table handler */
#define INCLUDE_DOSFS_DIR_VFAT  /* Microsoft VFAT dirent handler */
#define INCLUDE_DOSFS_DIR_FIXED /* 8.3 & VxLongNames directory handler */
#define INCLUDE_DOSFS_FMT       /* dosFs2 file system formatting module */
#define INCLUDE_DOSFS_CHKDSK    /* file system integrity checking */
#define INCLUDE_TCP_SHOW 

/*-------- added by chengxiang -------- end  */
#endif
/*
 * This define must be set to the value of the resonant oscillator
 * inserted in position U16 or the PCI freq of the ADS834x board.  
 * Choose from above list.
 */
#define	OSCILLATOR_FREQ	FREQ_33_MHZ

#define SYS_CLK_FREQ            FREQ_133_MHZ
#define	DEC_CLK_TO_INC		4	   /* # bus clks per increment*/ 
#define DEC_CLOCK_FREQ		SYS_CLK_FREQ /* Set to system default */

#define TPR 0x2000
#define LSRT_VALUE 0x32

#include "configAll.h"

#define DEFAULT_BOOT_LINE \
"tffs=0(0,0)host:/tffs0/app/mpu.bin h=192.168.1.200 e=192.168.1.100 u=suma pw=sumavision tn=ads8308 o=mottsec0"
#define FROM_FLASH_BOOT_LINE \
"tffs=0(0,0)host:/tffs0/app/mpu.bin h=192.168.1.200 e=192.168.1.100 u=suma pw=sumavision tn=ads8308 o=mottsec0"
#define	FROM_MPU_BOOT_LINE \
"mottsec(1,0)host:epu.bin h=192.168.254.9 e=192.168.254.4 u=suma pw=sumavision tn=ads8308 o=mottsec0"

#define INCLUDE_MMU_BASIC

#ifdef  INCLUDE_MMU_BASIC
#   define USER_I_MMU_ENABLE
#   define USER_D_MMU_ENABLE
#endif

#define INCLUDE_CACHE_SUPPORT

#ifdef  INCLUDE_CACHE_SUPPORT
#   define USER_D_CACHE_ENABLE
/* Does nothing about copyback vs writethrough in h/w, must use sysPhysMemDesc */
#   undef  USER_D_CACHE_MODE
#   define USER_D_CACHE_MODE  CACHE_COPYBACK | CACHE_SNOOP_ENABLE
#   define USER_I_CACHE_ENABLE
#   undef  USER_I_CACHE_MODE
#   define USER_I_CACHE_MODE  CACHE_COPYBACK
#endif

/* Number of TTY definition */

#undef	NUM_TTY
#define	NUM_TTY		N_SIO_CHANNELS	/* defined in ads827x.h */


/* Optional timestamp support */

#define INCLUDE_TIMESTAMP
#define INCLUDE_AUX_CLK

#undef INCLUDE_DMA

/* optional TrueFFS support */

#define  INCLUDE_TFFS

#ifdef INCLUDE_TFFS
#define INCLUDE_DOSFS	  /* dosFs file system */
#define INCLUDE_SHOW_ROUTINES /* show routines for system facilities*/
#endif /* INCLUDE_DOSFS */


/* clock rates */

#define	SYS_CLK_RATE_MIN	1	/* minimum system clock rate */
#define	SYS_CLK_RATE_MAX	8000	/* maximum system clock rate */
#define	AUX_CLK_RATE_MIN	1	/* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */


/* add on-chip drivers */
#undef INCLUDE_SECURITY_ENGINE /* only support if chip has E ie 8349E */

#undef INCLUDE_PIB_SUPPORT      /* include PIB IO board support */
#undef INCLUDE_PCI		/* include PCI library support */
#define INCLUDE_PCI

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000

#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000

/*#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000*/
#define CONFIG_SYS_PCIE1_IO_BASE		0xB1000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	       0x00800000

#ifdef  INCLUDE_PCI
#undef INCLUDE_PCI_AUTOCONF

/*
CPU Addr					PCI Addr
PCI_LOCAL_MEM_BUS	------------------------- PCI_MSTR_MEM_BUS
			-		        -
	      		-		        -
PCI_LOCAL_MEM_BUS +	------------------------- PCI_MSTR_MEM_BUS +
PCI_LOCAL_MEM_SIZE	----IMMR              	- PCI_MSTR_MEM_SIZE
      			-		        -
       			-		        -----PIMMR
	       		-		        -
		       	-		        -
CPU_PCI_MEM_ADRS	------------------------- PCI_MEM_ADRS
       		        -			-
		      	-			-
CPU_PCI_MEMIO_ADRS	------------------------- PCI_MEMIO_ADRS
	      	        -			-
		       	-		       	-
CPU_PCI_IO_ADRS		------------------------- PCI_IO_ADRS
		       	-	       		-
		       	-      			-
CPU_PCI_IO_ADRS +	------------------------- PCI_IO_ADRS +
CPU_PCI_IO_SIZE		-     			- PCI_IO_SIZE
		       	-     			-
		       	-     			-
		       	-     			-
		       	-------------------------- 4GBytes
*/



/* for custom sysPciAutoConfig.c */
#if 0

/* PCI based addresses */
#define PCI_MEM_ADRS		0x80000000
#define PCI_MEM_SIZE		0x1000000 		/*16MB */
#define PCI_MEM_SIZE_MASK	PCI_SIZE_256MB /* This should match PCI_MEM_SIZE */
#define PCI_MEMIO_ADRS		0x90000000
#define PCI_MEMIO_SIZE		0x10000000 		/*16MB */
#define PCI_MEMIO_SIZE_MASK     PCI_SIZE_256MB	/* This should match PCI_MEMIO_SIZE */
#define PCI_IO_ADRS	0xa0000000
#define PCI_IO_SIZE	0x10000000	/* IO Space is not available */


/* CPU based addresses */
#define CPU_PCI_MEM_ADRS		0x80000000
#define CPU_PCI_MEM_SIZE		PCI_MEM_SIZE
#define CPU_PCI_MEMIO_ADRS		0x90000000
#define CPU_PCI_MEMIO_SIZE		PCI_MEMIO_SIZE
#define CPU_PCI_IO_ADRS			0xa0000000
#define CPU_PCI_IO_SIZE			PCI_IO_SIZE


/* CPU from PCI bus */
#define PCI_MSTR_MEM_BUS		0x00000000
#define PCI_MSTR_MEM_SIZE		PCI_LOCAL_MEM_SIZE
#define PCI_BRIDGE_PIMMR_BASE_ADRS      0x40000000


/* CPU Address that is visible from PCI */
#define PCI_LOCAL_MEM_BUS	LOCAL_MEM_LOCAL_ADRS
#define PCI_LOCAL_MEM_SIZE	LOCAL_MEM_SIZE
/* This should at least match size of LOCAL_MEM_SIZE */
#define PCI_LOCAL_MEM_SIZE_MASK PCI_SIZE_256MB
#endif


#ifndef PCI_CFG_TYPE
#	ifdef INCLUDE_PCI_AUTOCONF
#		define PCI_CFG_TYPE PCI_CFG_AUTO
#	else
#		define PCI_CFG_TYPE PCI_CFG_FORCE
#	endif /* INCLUDE_PCI_AUTOCONF */
#endif /* PCI_CFG_TYPE */

#endif /* INCLUDE_PCI */


/* add necessary drivers */

#define INCLUDE_MOT_TSEC_END

#ifdef INCLUDE_MOT_TSEC_END
#ifndef INCLUDE_END
#define INCLUDE_END  /* only END-style driver for FCC */
#endif /* INCLUDE_END */
#endif /* INCLUDE_MOT_TSEC_END */

#ifdef INCLUDE_MOT_TSEC_END
#define INCLUDE_PRIMARY_TSEC_END      /* primary */
#define INCLUDE_SECONDARY_TSEC_END    /* secondary */      
#endif /* INCLUDE_MOT_TSEC_END */


#ifdef INCLUDE_PCI
#undef INCLUDE_FEI_END
#undef INCLUDE_GEI_END
#endif

#define INCLUDE_FLASH


#ifdef INCLUDE_FLASH
#  define SYS_FLASH_TYPE        FLASH_28F640J3A    /* flash device type */
#  define FLASH_WIDTH           2
#  define FLASH_CHIP_WIDTH      1
#  define FLASH_SEGMENT_SIZE    0x10000
#  define FLASH_ADRS            0xfffe0000
#  define FLASH_SIZE            FLASH_SEGMENT_SIZE
#  define FLASH_SIZE_WRITEABLE  FLASH_SEGMENT_SIZE
#  define NV_RAM_SIZE           FLASH_SEGMENT_SIZE
#  define FLASH_WIDTH_SPECIAL_2
#  undef FLASH_NO_OVERLAY
#  undef  NV_BOOT_OFFSET
#  define NV_BOOT_OFFSET        0

/* Add by xueyulong */
#define BOOT_LINE_OFFSET_NET		0
#define BOOT_LINE_OFFSET_FLASH	256
#define MACADDR_OFFSET	512
#define HWSN_OFFSET		518
#define BOOT_LINE_OFFSET_FROM_MPU    600
#define REBOOT_FLAG  856
#define FLASH_BOOTROM_VERSION_OFFSET    857
#define FLASH_BOOTROM_VERSION_LENGTH    6
#define BOOTROM_MAGIC					"TOPVISION_PN8600"
#define FLASH_BOOTROM_MAGIC_OFFSET      863
#define FLASH_BOOTROM_MAGIC_LENGTH		16
#define LEGAL_MAC1	0x00
#define LEGAL_MAC2	0x24
#define LEGAL_MAC3	0x68

/* Begin: Added by xueyulong, 2013/05/03, OLT-2274 */
#define FLASH_BOOT_PARAM			" Boot Param: %s "
#define FLASH_BOOT_PARAM_OFFSET		880
#define FLASH_BOOT_PARAM_LENGTH		512
#define FLASH_BOOT_PARAM_DEFAULT	" Boot Param: "
/* End: Added by xueyulong, 2013/05/03, OLT-2274 */

/* End of add */
#endif


#ifdef XGUA
#define FLASH_BASE_ADRS		0xD0010000
#define FLASH_MEN_SIZE      0x007F0000 /* 0x00800000    0x04000000*/
#else
#define FLASH_BASE_ADRS		0xD0000000
#define FLASH_MEN_SIZE      0x04000000
#endif
#define FLASH_WINDOW_SIZE	 FLASH_MEN_SIZE 

/*CPLD BANK2*/

#define CPLD_BASE_ADDR  0xF0000000
#define CPLD_SIZE  0x00100000


/* Memory addresses */

#define LOCAL_MEM_SIZE		    0x10000000		/* 256 Mbyte memory available */
#define LOCAL_MEM_LOCAL_ADRS	0x00000000		    /* Base of RAM */
#define SEGMENT_SIZE                  0x10000000        /*Max size of memory segment transtration is 256M*/

#define SECOND_SEG_START         0x10000000       /*Second segment memory start address*/
#define THIRD_SEG_START            0x20000000       /*third segment memory start address*/
#define FOURTH_SEG_START         0x30000000       /*fourth segment memory start address*/
/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
 * in config.h, MakeSkel, Makefile, and Makefile.*
 * All definitions for these constants must be identical.
 */

#define ROM_BASE_ADRS   0xFF800000		/* base address of ROM */
#define ROM_TEXT_ADRS  	ROM_BASE_ADRS + 0x100
#define ROM_SIZE       	0x100000		 /* ROM space */
#define ROM_WARM_ADRS   (ROM_TEXT_ADRS+8) /* warm reboot entry */


/* RAM address for ROM boot */
#define RAM_HIGH_ADRS  	0x03000000

/* RAM address for sys image */
#define RAM_LOW_ADRS	0x00010000

#define USER_RESERVED_MEM    0x00800000	/* user reserved memory size */

/* Hard Reset Configuration Words */

/* spmf 1:5 ie 5*66Mhz == 300Mhz CSB*/
#define HRCW_LOW_BYTE0  0x44   
/* Unknown corepll ratio probably 3 */
#define HRCW_LOW_BYTE1  0x06    
/* Must be cleared*/
#define HRCW_LOW_BYTE2  0x00
/* Must be cleared*/	
#define HRCW_LOW_BYTE3  0x00

/* Pci host,2* 32 bit buses,arbiters disabled */ 
#define HRCW_HIGH_BYTE0  0x04/*HRCW_HIGH_BMS_HIGH*/
/* Rom Location Flash 8 bit. Watch dog disabled  */
#define HRCW_HIGH_BYTE1  0x50 
/* MII */
#define HRCW_HIGH_BYTE2  0x00
/* Big Endian */
#define HRCW_HIGH_BYTE3  0x00  

/*
 * Default power management mode - selected via vxPowerModeSet() in
 * sysHwInit().
 */



#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

#include "ads8308.h" 			/* include the ads83xx params */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif	/* INCconfigh */
#if defined(PRJ_BUILD)
	#include "prjParams.h"
#endif
